1. FEILD OF INVENTION
The present invention relates to a method for fabricating a static random access memory (SRAM) polyload resistor. More particularly, the present invention relates to a method for fabricating a SRAM polyload resistor that utilizes lateral oxidation to reduce cross-sectional area in the load resistor region thereby increasing its resistance.
2. DESCRIPTION OF RELATED ART
In this electronic information age, SRAM is one of the most extensively used integrated circuit components in semiconductor manufacturing industry. Reduction of device dimensions without compromising quality so that more circuits can be packed inside a wafer is a common goal in the electronic industry. A load resistor is one major component in the fabrication of an SRAM cell. In general, a lightly doped or undoped polysilicon segment is used as a load resistor.
FIG. 1 is an equivalent circuit diagram of a conventional SRAM cell. As shown in FIG. 1, an SRAM cell comprises of two load resistors R.sub.1 and R.sub.2, two pull down transistors Q.sub.1 and Q.sub.2 and two access transistors Q.sub.3 and Q.sub.4. Transistors Q.sub.1, Q.sub.2, Q.sub.3 and Q.sub.4 utilize a first polysilicon layer as their gates. The high resistance portion of a second polysilicon layer acts as a load resistor, and the low resistance portion of the second polysilicon layer acts as an interconnect. In the conventional fabricating method, the same polysilicon layer is used to form interconnects as well as load resistors. To fabricate a segment of interconnect and a load resistor in the polysilicon layer, the specific segment for forming the interconnect is heavily doped or undoped. Then, an oxidation is performed on that particular segment where a load resistor is desired. Finally, the interconnect segment is heavily doped to lower its resistance. The interconnect and the load resistor together constitute a path for current to flow from power source V.sub.cc to node points A and B as shown in FIG. 1. The interconnect segments are thicker than the load resistor segments because the same polysilicon layer (that is, the second polysilicon layer) is used to form interconnects and load resistors.
To better understand the method and defects in the fabrication of a SRAM polyload resistor, an example is given below with reference to FIGS. 2A through 2P.
FIGS. 2A through 2P are cross-sectional views showing the progression of manufacturing steps in fabricating SRAM polyload resistor according to a conventional method.
First, as shown in FIG. 2A, a semiconductor substrate 110 is provided. Then, a conventional method is used to form a transistor in the substrate 110. The transistor comprises a gate 112, a gate dielectric layer 111 and N.sup.+ source/drain regions 114 and 116. Thereafter, a dielectric layer 118 is formed over the semiconductor substrate.
Next, as shown in FIG. 2B, a patterned first photoresist layer 120 is formed over the dielectric layer 118 exposing a portion of the dielectric layer 118 above the source/drain region 114 and the gate 112.
Next, as shown in FIG. 2C, the exposed dielectric layer 118 is etched to form vias above the source/drain region 114 and the gate 112.
Thereafter, as shown in FIG. 2D, the first photoresist layer 120 is removed.
Subsequently, as shown in FIG. 2E, a polysilicon layer 60 is formed over the dielectric layer 118. Polysilicon layer 60 is then doped with ions to adjust its resistance, as shown in FIG. 2F. However, for some conventional fabricating methods, ion doping is deferred to a later stage.
Next, as shown in FIG. 2G, using photolithographic processing, a patterned second photoresist layer 62 is formed over the polysilicon layer 60 exposing a portion of the polysilicon layer 60 that needs to be removed.
Next, as shown in FIG. 2H, the exposed portion of the polysilicon layer 60 is etched to remove a segment of polysilicon layer 60 located between the source/drain region 114 and the gate 112, thereby forming an open circuit.
Next, as shown in FIG. 2I, the second photoresist layer 62 is removed. Subsequently, as shown in FIG. 2J, a chemical vapor deposition method is used to deposit a layer of silicon nitride at least covering the polysilicon layer 60. The silicon nitride layer serves as an anti-oxidation layer 64 serving a protective function.
Next, as shown in FIG. 2K, a patterned third photoresist layer 66 is formed over the anti-oxidation layer 64 exposing a portion of the anti-oxidation layer 64 that needs to be removed.
Thereafter, a shown in FIG. 2L, the exposed portion of the anti-oxidation layer 64 is etched away. Then, as shown in FIG. 2M, the third photoresist layer 66 is removed.
Next, as shown in FIG. 2N, a local oxidation of silicon (LOCOS) method is used to form a thermal oxidation layer 68 on the exposed polysilicon layer 60. During thermal oxidation, only the polysilicon layer segment not covered by an anti-oxidation layer will react. Consequently, the thickness of the polysilicon layer 60 underneath the thermally oxidized layer 68 will be reduced, and hence a load resistor segment 70 is formed. Furthermore, lateral oxidation will also take place during the thermal oxidation, and the width of the polysilicon layer 60 will be reduced as well.
Next, as shown in FIG. 20, the anti-oxidation layer 64 is removed. Finally, as shown in FIG. 2P, ions are implanted into part of polysilicon layer 60 whose surface is not covered by any thermally oxidized layer 68, thereby lowering its resistance and forming the interconnect segment 72.
The above method of fabricating SRAM load resistor utilizes the same polysilicon layer so that interconnects are formed by heavily doping the desired segments, and the load resistor segments are formed by a LOCOS method covering the desired polysilicon segment so that the polysilicon below gets thinner. Therefore, a high load resistor is obtained without affecting the interconnect segments. However, one defect is that during local oxidation of the silicon, beside oxidation in the vertical dimension, oxidation also occurs in the lateral dimension. Hence, the thickness of underlying polysilicon layer and the lateral dimension will both be reduced. This can easily lead to circuit opening. Furthermore, the steps necessary for forming interconnects and load resistor according to the conventional method are quite complicated as well.
In light of the foregoing, there is a need to provide an improved method of forming interconnects and load resistors.